VLSI & FPGA IEEE 2013-14 Project Titles

VLSI & FPGA PROJECTS 2013-2014 
VLSI Projects using Spartan3 FPGA Kit (Spartan3AN FPGA Kit / Xilinx ISE / Xilinx EDK) 

* A 10-T SRAM cell with Inbuilt Charge Sharing for Dynamic Power Reduction

* A Current-Starved Inverter-based Differential Amplifier Design for Ultra-Low Power Applications

* A Fast Low-Light Multi-Image Fusion with Online Image Restoration

* A High Performance D-Flip Flop Design with Low Power Clocking System using MTCMOS

* A Low Power Fault Tolerant Reversible Decoder using MOS Transistor

* A Low Power Single Phase Clock Distribution using VLSI technology

* A Novel modulo Adder for 2n-2k-1 Residue Number System

* A Novel Transistor Level Realization of Ultra Low Power High-Speed Adiabatic Vedic Multiplier

* A Topology-Based Model for Railway Train Control Systems

* Achieving Reduced Area By Multi-Bit Flip Flop Design

* An Analysis of SOBEL and GABOR Image Filters for Identifying Fish

* An Efficient Denoising Architecture for Removal of Impulse Noise in Images

* An Efficient High Speed Wallace Tree Multiplier

* An Efficient SQRT Architecture of Carry Select Adder Design by Common Boolean Logic

* An Interactive RFID-based Bracelet for Airport Luggage Tracking System

* Area-Delay Efficient Binary Adders in QCA

* Asynchronous Design of Energy Efficient Full Adder

* Background Subtraction Based on Threshold detection using Modified K-Means Algorithm

* Comparison of Static and Dynamic Printed Organic Shift Registers

* CORDIC based Fast Radix-2 DCT Algorithm

* Design and Implementation of 32 Bit Unsigned Multiplier Using CLAA and CSLA

* Design Flow for Flip-Flop Grouping in Data-Driven Clock Gating

* Design of Digit-Serial FIR Filters: Algorithms, Architectures and a CAD Tool

* Design of High Speed Low Power Viterbi Decoder for TCM System

* Design of Low Energy, High Performance Synchronous and Asynchronous 64-Point FFT

* Design of Low Power Sequential Circuit Using Clocked Pair Shared Flip flop

* FFT Architectures for Real-Valued Signals Based on Radix-2by3 & Radix-2by4 Algorithms

* Fixed-Width Multipliers and Multipliers- Accumulators with Min-Max Approximation Error

* FPGA Implementation of Pipelined Architecture For SPIHT Algorithm

* Gate Mapping Automation for Asynchronous NULL Convention Logic Circuits

* Hardware Implementation of a Digital Watermarking System for Video Authentication

* High-Throughput Compact Delay-Insensitive Asynchronous NOC Router

* High-Throughput Multi standard Transform Core Supporting MPEG/H.264/VC-1 using Common Sharing Distributed Arithmetic

* Improvement of the Security of Zigbee by a New Chaotic Algorithm

* Least Significant Bit Matching Steganalysis based on Feature Analysis

* Location-Aware and Safer Cards: Enhancing RFID Security and Privacy via Location Sensing

* Low Latency Systolic Montgomery Multiplier for Finite Field Based on Pentanomials

* Low-Complexity Multiplier for GF (2m) based on All-One Polynomials

* Low-Overhead Fault-Tolerance Technique for a Dynamically Reconfigurable Soft-core Processor

* Low-Power Digital Signal Processing Using Approximate Adders

* Low-Power, High-Throughput and Low-Area Adaptive FIR Filter based on Distributed Arithmetic

* Memory efficient high-Speed convolution-based generic structure for multilevel 2D DWT

* Modified Gradient Search for Level Set Based Image Segmentation

* Multicarrier Systems based on Multistage Layered IFFT Structure

* Optical Flow Estimation for Flame Detection in Videos

* Parallel AES Encryption Engines for Many-Core Processor Arrays

* Performance Analysis of a New CMOS Output Buffer

* Performance Evaluation of FFT Processor Using Conventional and Vedic Algorithm

* Pipelined Radix-2k Feed forward FFT Architectures

* Prototype of a Fingerprint Based Licensing System For Driving

* Real Time Communication between Multiple FPGA Systems in Multitasking Environment Using RTOS

* Reconfigurable Processor for Binary Image Processing

* Reduced-Complexity LCC Reed–Solomon Decoder based on Unified Syndrome Computation

* Reduction of Leakage Current and Power in Full Subtractor Using MTCMOS Technique

* Reverse Circle Cipher for Personal and Network Security

* RFID-based Location System for Forest Search and Rescue Missions

* RFID-based Tracking System Preventing Trees Extinction and Deforestation

* Satellite Image Enhancement Using Discrete Wavelet Transform and Threshold Decomposition Driven Morphological Filter

* Secure Transmission in Downlink Cellular Network with a Cooperative Jammer

* Segmentation and Location of Abnormality in Brain MR Images using Distributed Estimation

* Selective Eigen background for Background Modeling & Subtraction in Crowded Scenes

* Shadow Removal for Background Subtraction Using Illumination Invariant Measures

* Teaching HW/SW Co-Design with a Public Key Cryptography Application

* Test Patterns of Multiple SIC Vectors: Theory and Application in BIST Schemes

* The Security Technology and Tendency of New Energy Vehicle in Future  

FINAL YEAR PROJECTS 2013 - 2014

 Why NCCT 

Complete Guidance * On time Completion * Excellent Support * Multi platform Training * Flexibility 

PROJECTS SUPPORTS & DELIVERABLES

· Project Abstracts

· IEEE Paper, Project IEEE Base / Reference Paper

· Project Block Diagram

· Project Circuit Diagram 

· PPT & Review preparation for Viva 

· Project Report Guidance 

· Project Demo & Explanation

· Working Procedure & Screen Shots 

· Datasheets, Manuals & Reference Books in DVD 

· Project Kit, * “VLSI Hardware Kit” * 

· Project Acceptance / Completion Certificate 

VLSI PROJECTS USING 
VLSI Projects using Spartan3 FPGA Kit (Spartan3AN FPGA Kit / Xilinx ISE / Xilinx EDK)Embedded Projects using VLSI FPGA Spartan Processors (Spartan3 FPGA Kit / Xilinx ISE  / Xilinx EDK)

 VLSI PROJECT DOMAINS 
COMMUNICATION SYSTEMS, ARCHITECTURAL DESIGN, PROTOCOL DESIGN, LOW POWER DESIGN, IMAGE PROCESSING, STEGANOGRAPHY, SURVEILLANCE SYSTEMS, CRYPTOGRAPHY, SOFTCORE PROCESSOR DESIGN, REAL TIME AUDIO / VIDEO PROCESSING, SECURITY PROTOCOLS, POWER ANALYZER

VLSI PROJECT TITLES
FINAL YEAR PROJECTS, IEEE PROJECTS 2012

2012 IEEE VLSI PROJECT TITLES

VLSI IMAGE PROCESSING PROJECT TITLES   
· A Pipeline VLSI Architecture for Fast Computation of the 2-D Discrete Wavelet Transform           
· An Efficient Denoising Architecture for Removal of Impulse Noise in Images               
· Chaos-Based Security Solution for Fingerprint Data During Communication and Transmission       
· Cognition and Removal of Impulse Noise With Uncertainty           
· Design and Implementation of a Pipelined Datapath for High-Speed Face Detection Using FPGA       
· Fast Higher-Order MR Image Reconstruction Using Singular-Vector Separation            
· Interference Removal Operation for Spread Spectrum Fingerprinting Scheme               
· New Families of Fourier Eigen functions for Steerable Filtering   
· Robust Watermarking of Compressed and Encrypted JPEG2000 Images                       

VLSI COMMUNICATION SYSTEMS PROJECT TITLES   
· A Novel Filter-Bank Multicarrier Scheme to Mitigate the Intrinsic Interference Application to MIMO Systems                       
· A Wideband Digital RF Receiver Front-End Employing a New Discrete-Time Filter for m-WiMAX                               
· Cooperative Beamforming for Cognitive Radio Networks-A Cross-Layer Design            · Curvature Based ECG Signal Compression for Effective Communication on WPAN               
· Distributed Coordination Protocol for Ad Hoc Cognitive Radio Networks  · Dynamic Resource Allocation in MIMO-OFDMA Systems with Full-Duplex and Hybrid Relaying             
· Good Synchronization Sequences for Permutation Codes           
· High-Throughput Soft-Output MIMO Detector Based on Path-Preserving Trellis-Search Algorithm                               
· Low Complexity Transmitter Architectures for SFBC MIMO-OFDM Systems                    
· Low-Complexity Iterative Channel Estimation for Turbo Receivers
· Novel Interpolation and Polynomial Selection for Low-Complexity Chase Soft-Decision Reed-Solomon Decoding                       
· Power Management of MIMO Network Interfaces on Mobile Systems  

· Reconfigurable Adaptive Singular Value Decomposition Engine Design for High-Throughput MIMO-OFDM Systems           
· Spectrum Sensing in the Presence of Multiple Primary Users       
· Synthesis and Array Processor Realization of a 2-D IIR Beam Filter for Wireless Applications                               
· The Design of Hybrid Asymmetric-FIR_Analog Pulse-Shaping Filters Against Receiver Timing Jitter                               
· Transmission of 4-ASK Optical Fast OFDM With Chromatic Dispersion Compensation                                       
· VLSI Architecture for a Reconfigurable Spectrally Efficient FDM Baseband Transmitter                                   

VLSI AUDIO/SPEECH SIGNAL PROCESSING PROJECT TITLES       
· A Low-Complexity Design for an MP3 Multi-Channel                   
· A Wiener Filter Approach to Microphone Leakage Reduction in Close-Microphone Applications                   
· Enhancement of Single-Channel Periodic Signals in the Time-Domain                             
· Musical-Noise-Free Speech Enhancement Based on Optimized Iterative Spectral Subtraction                       
· Speaker and Noise Factorization for Robust Speech Recognition   
· State-Space Frequency-Domain Adaptive Filtering for Nonlinear Acoustic Echo Cancellation                   
· Telephone Channel Compensation in Speaker Verification Using a Polynomial Approximation in the Log-Filter-Bank Energy Domain   

VLSI CRYPTOGRAPHY PROJECT TITLES       
· A Fast Cryptography Pipelined Hardware developed in FPGA with VHDL
· A Formal Approach to Designing Cryptographic Processors Based on GF(2^m) Arithmetic Circuits                   
· A Novel Architecture for VLSI Implementation of RSA Cryptosystem
· An efficient FPGA implementation of the Advanced Encryption Standard algorithm
· Construction of Optimum Composite Field Architecture for Compact High-Throughput AES S-Boxes                   
· Efficient FPGA Implementations of Point Mult on Binary Edwards & Generalized Hessian Curves Using               
· FPGA Hardware of the LSB Steganography Method
· Secure Multipliers Resilient to Strong Fault-Injection Attacks Using Multilinear Arithmetic Codes               
· VHDL Implementation of a Flexible and Synthesizable FFT Processor

VLSI SIGNAL PROCESSING PROJECT TITLES   
· A Highly-Digital VCO-Based ADC Using Phase Interpolator & Digital Calibration            
· A Low-Power Low-Cost Design of Primary Synchronization Signal Detection                
· A Novel Approach for Motion Artifact Reduction in PPG Signals Based on AS-LMS Adaptive Filter                   
· A Single-Pass-Based Localized Adaptive Interpolation Filter for Video Coding               
· Area-Efficient Parallel FIR Digital Filter Structures for Symmetric Convolutions Based on Fast FIR Algorithm           
· Area-Efficient VLSI Implementation for Parallel Linear-Phase FIR Digital Filters of Odd Length Based on Fast FIR Algorithm   
· Design and Simulation of 32-Point FFT Using Radix-2 Algorithm for FPGA Implementation
· Design of Digit-Serial FIR Filters Algorithms, Architectures, and a CAD Tool                 
· Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic                       
· Implementation of PSK and QAM demodulators on FPGA
· On the BIBO Stability Condition of Adaptive Recursive FLANN Filters With Application to Nonlinear Active Noise Control       
· Pipelined Parallel FFT Architectures via Folding Transformation         
· Platform-Independent Customizable UART Soft-Core
· Real Time Hardware Co-simulation of Edge Detection for Video Processing System
· Resource-Efficient FPGA Architecture and Implementation of Hough Transform           
· VLSI Architecture of Arithmetic Coder Used in SPIHT

VLSI POWER ELECTRONICS CONTROL PROJECT TITLES       
· Design and Implementation of a New Multilevel Inverter Topology
· Digital Filters for Fast Harmonic Sequence Component Separation 3Ph                           
· Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic                   
· A Filter Bank and a Self-Tuning Adaptive Filter for the Harmonic and Inter harmonic Estimation in Power Signals       
· Fully FPGA-Based Sensorless Control for Synchronous AC Drive Using an Extended Kalman Filter               
· Synchronous FPGA-Based High-Resolution Implementations of Digital Pulse-Width Modulators               

VLSI LOW POWER DESIGN PROJECT TITLES
· Design of Low Voltage Low Power Operational Amplifier  
· Enhanced Power Gating Schemes for Low Leakage Low Ground Bounce Noise in Deep Submicron Circuits
· Low-Power Pulse-Triggered Flip-Flop Design With Conditional Pulse-Enhancement Scheme
· Low-Swing Differential Conditional Capturing Flip-Flop for LC Resonant Clock Distribution Networks
· Reactivation Noise Suppression With Sleep Signal Slew Rate Modulation in MTCMOS Circuits
· Single Phase Clocked Quasi Static Adiabatic Tree Adder
· Ultralow-Voltage Process-Variation-Tolerant Schmitt-Trigger-Based SRAM Design

VLSI SECURITY & SYSTEM GENERATOR PROJECT TITLES
· A Novel Non-payment Vehicle Searching Method for Multilane-Free-Flow Electronic-Toll-Collection Systems
· Design of Intelligent Home Appliance Control System Based on FPGA and ZIGBEE
· Implementation of a Home Automation System through a Central FPGA Controller
· New Clock Generation Techniques for Synchronous Sampling of 16-QAM RF Signals
· Real Time Smart Car Lock Security System Using Face Detection and Recognition
· Simulation and Implementation of a BPSK Modulator on FPGA


Why NCCT
Complete Guidance * On time Completion * Excellent Support * Multi platform Training * Flexibility

PROJECTS SUPPORTS & DELIVERABLES
· Project Abstracts & IEEE Paper
· Project Block Diagram & Circuit Diagram
· Datasheets and Manuals
· PPT & Review Details Guidance
· Project Report Guidance
· Working Procedure & Screen Shots
· Materials & Reference Books in DVD
· Project Completion Certificate


Embedded System / Electronics / Hardware Projects using
# Embedded Projects using Atmel Microcontrollers (Atmel 89c51/52, Keil C / Assembly, VB)
# Embedded Projects using ARM (ARM 7 / keil / VB)
# Embedded Projects using VLSI FPGA Spartan Processors (Spartan3 FPGA Kit / Xilinx ISE  / Xilinx EDK)
# Embedded Projects using PIC Microcontrollers (PIC16F877 / MPLAB / PICC / VB)
# VLSI Projects using Spartan3 FPGA Kit (Spartan3AN FPGA Kit / Xilinx ISE / Xilinx EDK)
# DSP Projects using AD-BlackFin Processors (BF531 / Visual DSP++)
# Power Electronics Projects using Microcontroller with Matlab Simulation
# Power Electronics Projects without Microcontrollers with Matlab Simulation
# Power Systems Projects using Matlab Simulation